21 March 2024
- 02:0102:01, 21 March 2024 diff hist +24 Level/Wire Spaghetti No edit summary current Tag: Visual edit: Switched
- 01:5601:56, 21 March 2024 diff hist +43 N File:WikiRegisterGroupa-remake-decode-result.png No edit summary current
- 01:5501:55, 21 March 2024 diff hist +43 N File:WikiRegisterGroupa-remake-decode-arg.png No edit summary current
- 01:5301:53, 21 March 2024 diff hist +43 N File:WikiRegisterGroupa-remake.png No edit summary current
19 March 2024
- 13:5513:55, 19 March 2024 diff hist +1,815 N Level/Wire Spaghetti Created page with "In this level, we need to build a CPU based on the LEG architecture. This is a significant milestone and quite a challenging one (it took me 20 hours to figure it out at the time). File:Leg.png I propose a feasible implementation solution: Firstly, I encapsulated the register group. Below is a component called "WikiRegisterGroup." It's important to note that a modified register is utilized here. File:RegisterPlus.png The above has two input signals. The firs..." Tag: Visual edit: Switched
- 13:0113:01, 19 March 2024 diff hist +23 N File:Leg Counter.png No edit summary current
- 13:0013:00, 19 March 2024 diff hist +23 N File:Leg ConnectRES.png No edit summary current
- 12:5812:58, 19 March 2024 diff hist +46 N File:Leg ReadInput.png No edit summary current
- 12:5612:56, 19 March 2024 diff hist +44 N File:Leg ConnectBus.png No edit summary current
- 12:5312:53, 19 March 2024 diff hist +19 N File:Leg BaseLine.png No edit summary current
- 12:5212:52, 19 March 2024 diff hist +22 N File:WikiRegisterGroup DecodeRes.png No edit summary current
- 12:5212:52, 19 March 2024 diff hist +43 N File:WikiRegisterGroup DecodeArg.png No edit summary current
- 12:5012:50, 19 March 2024 diff hist +19 N File:WikiRegisterGroup Bus.png No edit summary current
- 12:4712:47, 19 March 2024 diff hist +30 N File:RegisterPlus.png No edit summary current
- 12:0812:08, 19 March 2024 diff hist +16 N File:Leg.png No edit summary current
