Known issues/2.0.16

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This page descibes the early access verion 2.0.16 apha. It may not be completely correct for the the current stable version, nor the latest unstable version. Help us update it, and you get a cookie.

A number of levels in version are known to be broken, and require some workarounds to complete. Some of thes issues affect multiple levels, I only give the first level you are likely to come across them.

Symphony Counter

Missing bit-width tool and 16-bit

You should be able to place 16-bit components, but the bit-width tool might not be present in the level.

Some people report that the bit-width tool appears simply by going to the Sandbox then component factory.

If that does not work you can copy-paste 16-bit components from the sandbox.

Wire Spaghetti

RAM broken in Wire Spaghetti

Various issues with RAM in Wire Spaghetti and following levels.

These stem from the lack of API in text.si to identify which RAM block is the program and which is the register file.

WORKAROUNDS:

1. Copy-paste a 16-bit RAM from sandbox for the register file, then
2. Copy-paste a 32-bit RAM from sandbox for the program.
3. These steps should be taken in order. This might take several attempts, for reasons that are unclear to me.

Wire Spaghetti level log out of date

The level log for Wire Spaghetti states: 3. Click "Edit link components" on the program component and then "Add register file". (do not connect the zr register)

This is now wrong, zr should be linked, as part of the register file.

RAM is byte addressed

The level log does not make clear that RAM is byte addressed (this is a change from 0.1059).

Since the register file entries are 16-bits (2 bytes) wide the register address should be adjusted to match.

r9 should have value 65535 not 0

If you see this error on tick 62, then you are writing to and reading from the zero register, this is an error in your circuit, not a bug in the game.

Integrating ALU

The ALU you previous built has a multipy instruction. The tests for Integrating ALU assume mul returns zero.

WORKARND: Delete or otherwise disable the multiply componet inside the ALU custom component.

RAM

The level log is incomplete.

There are 4 new instructions:

• store_16
• load_16
• store_8
• load_8

The level log incorrectly states put the store port at the top, they should (for this level) be at the bottom.

WORKAROUND: Add to the existing program block from bottom to top:

1. a 16-bit store port, then
2. an 8-bit store.
3. Move the existing 32 bit load port above the store ports, followed by
4. a 16-bit load port, and
5. an 8-bit load port.

Instruction aliases

Level fails to compile due to wrong meta.txt

Edit Turing Complete\campaign\symphony_9_aliases\meta.txt and delete the last 4 lines of default_assembly, so that the section reads

default_assembly = `
in r1
mov r2, r1
neg r3, r2
not r4, r2
`

Level fails due to wrong test.si

Edit Turing Complete\campaign\symphony_9_aliases\test.si and replace the it all with

def get_input($scratch_space: [Int], tick: Int, $inputs: [Int]) {
    inputs[0] = 10
}

def check_output($scratch_space: [Int], tick: Int, inputs: [Int], outputs: [Int]) TestResult {
    switch tick
        0 {
            if get_register_value(1) != 10 {
                set_error(`The first instruction is supposed to move the input value (10) to r1.`)
                return fail
            }
        }
        1 {
            if get_register_value(2) != 10 {
                set_error(`The first instruction is supposed to move the input value (10) to r2.`)
                return fail
            }
        }
        2 {
            if get_register_value(3) != 65526 {
                set_error(`Negate r2 and store the result (65526) in r3.`)
                return fail
            }
        }
        3 {
            if get_register_value(4) != 65525 {
                set_error(`NOT r2 and store the result (-9) in r4.`)
                return fail
            }
            return win
        } 
}

Various levels

A number of levels' meta.txt have out of date spec.isa, these can be fixed with a simple regex

s/(^|  )([01][01])0/$10$2/g