Toggle search
Search
Toggle menu
notifications
Toggle personal menu
Editing
Save breaker changes
(section)
From Turing Complete
Views
Read
Edit
Edit source
View history
associated-pages
Page
Discussion
More actions
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
=== ROM === The old {{Component|ROM}} has been removed to get the same behavior place an {{Component|SSD}} and a load port. As of version 2.0.10 this configuration will be (mis-)labeled as RAM. If you want to write to it in sandbox, you can also include a store port. The load port must be '''above''' the store port to recover the same behavior has before. There is no way to configure a RAM or Latency RAM component so that it is writable ''only'' in sandbox.
Summary:
Please note that all contributions to Turing Complete are considered to be released under the Creative Commons Attribution-ShareAlike (see
TuringComplete:Copyrights
for details). If you do not want your writing to be edited mercilessly and redistributed at will, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource.
Do not submit copyrighted work without permission!
Cancel
Editing help
(opens in new window)
