A wire segment equalizes the signal between two wire nodes, and a wire node equalizes the signal between several wire segments and component i/o. If they cannot equalize the signal (for example if two component outputs are connected and one of them is 164 and the second one is 17, a conflict will happen. In real life when a conflict happens there will be
- lots of current, which means lots of heat
- failure of attempt to be bistable (i.e converging onto a certain binary value, instead of somewhere in between)
TC reports a Short Circuit error and stops the clock/simulation in this case, because it is usually an undesired outcome unless you know how the transistors work, and you are working with an analog circuit rather than a digital one.
A wire node/segment can carry a value or not (not carrying a value is also called Hi-Z where Z means impedance. When "this (bundle of) wire has a lot of impedance" is the most you can specify, it won't be carrying a value, otherwise you would be saying that value). When it is not carrying a value, other things can overwrite it. Wires start at Hi-Z state until connected.
Although in real life a bundle of wires can have some wires Hi-Z and some others tied to a certain potential (having value), it is undesired when the bundle of wires represents a number or anything that only represents one thing. So TC doesn't allow that. Additionally, TC makes all Hi-Z 0 if fed into/out of a component (for example, when inputting to most parts, outputting from a non-switching output, or a switched on switching output).