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* {{Component|2-bit decoder||alpha}} | * {{Component|2-bit decoder||alpha}} | ||
* {{Component|3-bit decoder||alpha}} | * {{Component|3-bit decoder||alpha}} | ||
* {{Component|Delay line||alpha}} | |||
* {{Component|Register||alpha}} | * {{Component|Register||alpha}} | ||
=== Logical operations === | === Logical operations === | ||
* {{Component|NOT||alpha}} | * {{Component|NOT||alpha}} | ||
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== Word components == | == Word components == | ||
* {{Component|Constant (word)|Constant|alpha}} | |||
* {{Component|Switch (word)|Switch|alpha}} | * {{Component|Switch (word)|Switch|alpha}} | ||
* {{Component|MUX (word)|MUX|alpha}} | * {{Component|MUX (word)|MUX|alpha}} | ||
* {{Component| | * {{Component|Delay line (word)|Delay line|alpha}} | ||
* {{Component|Register (word)|Register|alpha}} | * {{Component|Register (word)|Register|alpha}} | ||
* {{Component|Counter (word)|Counter|alpha}} | * {{Component|Counter (word)|Counter|alpha}} | ||
=== Logical operations === | === Logical operations === | ||
* {{Component|ROR (word)|ROR (rotate right)|alpha}} | * {{Component|ROR (word)|ROR (rotate right)|alpha}} | ||
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* {{Component|Static evaluator||alpha}} | * {{Component|Static evaluator||alpha}} | ||
* {{Component|Configurable delay||alpha}} | * {{Component|Configurable delay||alpha}} | ||
=== Verilog ({{Console|dev_mode|on}}) === | |||
* {{Component|Verilog input||alpha}} | |||
* {{Component|Verilog output||alpha}} | |||
== Level creation (DEV) components ({{Console|dev_mode|on}}) == | |||
* {{Component|Level component (dev)|Level component|alpha}} | |||
=== Probes === | |||
* {{Component|Wire probe (dev)|Wire probe (bit)|alpha}} | |||
* {{Component|Wire probe (word) (dev)||alpha}} | |||
* {{Component|Memory probe (dev)|Memory probe (bit)|alpha}} | |||
* {{Component|Memory probe (word) (dev)||alpha}} | |||
=== Input === | |||
* {{Component|1-bit input (dev)|1-bit input|alpha}} | |||
* {{Component|1-bit input (value) (dev)|1-bit input for custom components with value|alpha}} | |||
* {{Component|1-bit input (message) (dev)|1-bit input for custom components with message|alpha}} | |||
* {{Component|2-bit input (dev)|2-bit input|alpha}} | |||
* {{Component|3-bit input (dev)|3-bit input|alpha}} | |||
* {{Component|4-bit input (dev)|4-bit input|alpha}} | |||
* {{Component|Word input (dev)|Word input|alpha}} | |||
* {{Component|Word input (message) (dev)|Word input with message}} | |||
* {{Component|Word input (switched) (dev)|Word input with enable pin}} | |||
=== Output === | |||
* {{Component|1-bit output (dev)|1-bit output|alpha}} | |||
* {{Component|1-bit output (sum) (dev)|1-bit output with SUM label|alpha}} | |||
* {{Component|1-bit output (carry) (dev)|1-bit output with CAR label|alpha}} | |||
* {{Component|1-bit output (value) (dev)|1-bit output with value|alpha}} | |||
* {{Component|2-bit output (dev)|2-bit output}} | |||
* {{Component|3-bit output (dev)|3-bit output}} | |||
* {{Component|3-bit output (value) (dev)|3-bit output with value|alpha}} | |||
* {{Component|4-bit output (dev)|4-bit output|alpha}} | |||
* {{Component|Word output (dev)|Word output}} | |||
* {{Component|Word output (switched) (dev)|Word output with enable pin}} | |||
=== Memory === | |||
* {{Component|Delay line (dev)|Delay line (bit)|alpha}} | |||
* {{Component|Delay line (word) (dev)|Delay line (word)|alpha}} | |||
* {{Component|Register (dev)|Register (bit)|alpha}} | |||
* {{Component|Register (word) (dev)|Register (word)|alpha}} | |||
Revision as of 06:49, 14 January 2025
A list of components found in the game, updated for the alpha branch.
Bit components
- Constant ON
- Constant OFF
- Switch
- Full adder
- 1-bit decoder
- 2-bit decoder
- 3-bit decoder
- Delay line
- Register
Logical operations
Splitters and Makers
Word components
Logical operations
- ROR (rotate right)
- ROL (rotate left)
- ASR (arithmetic shift right)
- LSR (logical shift right)
- LSL (logical shift left)
- NOT
- AND
- OR
- NAND
- NOR
- XOR
- XNOR
Mathematical operations
- LESS (signed less than)
- LOW (unsigned less than)
- EQ (equality)
- MUL (multiplication)
- MOD (remainder after division)
- DIV (division)
- INC (add 1)
- ADD (addition)
- NEG (negation)
Splitters and makers
IO components
Level components
Component factory
Probes
Memory
Display
Input (IO)
Advanced
Verilog (dev_mode on )
Level creation (DEV) components (dev_mode on )
Probes
Input
- 1-bit input
- 1-bit input for custom components with value
- 1-bit input for custom components with message
- 2-bit input
- 3-bit input
- 4-bit input
- Word input
- Word input with message
- Word input with enable pin
Output
- 1-bit output
- 1-bit output with SUM label
- 1-bit output with CAR label
- 1-bit output with value
- 2-bit output
- 3-bit output
- 3-bit output with value
- 4-bit output
- Word output
- Word output with enable pin