Level/Wire Spaghetti - Revision history

Tabbleman at 02:01, 21 March 2024

2024-03-21T02:01:58Z

← Older revision		Revision as of 02:01, 21 March 2024
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	The above has two input signals. The first one controls whether the register outputs to the first bus, and the second one controls whether it outputs to the second bus.		The above has two input signals. The first one controls whether the register outputs to the first bus, and the second one controls whether it outputs to the second bus.
			[[File:WikiRegisterGroupa-remake.png]]
	[[File:~~WikiRegisterGroup Bus~~.png]]

	This component also accepts an input called "INPUT," which can be used to write to the corresponding register based on the value of "res."		This component also accepts an input called "INPUT," which can be used to write to the corresponding register based on the value of "res."
	Then, the parameters 1 and parameters 2 are decoded, while the program counter and IN/OUT are separately extracted.		Then, the parameters 1 and parameters 2 are decoded, while the program counter and IN/OUT are separately extracted.

	[[File:~~WikiRegisterGroup DecodeArg~~.png]]		[[File:WikiRegisterGroupa-remake-decode-arg.png]]


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	[[File:~~WikiRegisterGroup DecodeRes~~.png]]		[[File:WikiRegisterGroupa-remake-decode-result.png]]

1.163.210.239: add missing guide

2024-03-20T08:07:31Z

add missing guide

← Older revision		Revision as of 08:07, 20 March 2024
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	Finally, we connect the value of the program counter to the bus.
			Finally, we connect the value of the program counter to the bus and enable RegisterGroup and AlU.



	[[File:Leg Counter.png]]		[[File:Leg Counter.png]]

Tabbleman: Created page with "In this level, we need to build a CPU based on the LEG architecture. This is a significant milestone and quite a challenging one (it took me 20 hours to figure it out at the time). File:Leg.png I propose a feasible implementation solution: Firstly, I encapsulated the register group. Below is a component called "WikiRegisterGroup." It's important to note that a modified register is utilized here. File:RegisterPlus.png The above has two input signals. The firs..."

2024-03-19T13:55:26Z

Created page with "In this level, we need to build a CPU based on the LEG architecture. This is a significant milestone and quite a challenging one (it took me 20 hours to figure it out at the time). File:Leg.png I propose a feasible implementation solution: Firstly, I encapsulated the register group. Below is a component called "WikiRegisterGroup." It's important to note that a modified register is utilized here. File:RegisterPlus.png The above has two input signals. The firs..."

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In this level, we need to build a CPU based on the LEG architecture. This is a significant milestone and quite a challenging one (it took me 20 hours to figure it out at the time).

[[File:Leg.png]]

I propose a feasible implementation solution: Firstly, I encapsulated the register group. Below is a component called "WikiRegisterGroup."
It's important to note that a modified register is utilized here.

[[File:RegisterPlus.png]]

The above has two input signals. The first one controls whether the register outputs to the first bus, and the second one controls whether it outputs to the second bus.

[[File:WikiRegisterGroup Bus.png]]

This component also accepts an input called "INPUT," which can be used to write to the corresponding register based on the value of "res."
Then, the parameters 1 and parameters 2 are decoded, while the program counter and IN/OUT are separately extracted.

[[File:WikiRegisterGroup DecodeArg.png]]

The addresses where the results are stored are also decoded, and the corresponding counters and output pins are printed out.

[[File:WikiRegisterGroup DecodeRes.png]]

Assuming you have already completed an ALU with addition functionality, let's proceed from the following diagram:

[[File:Leg BaseLine.png]]

We put the result computed by the ALU onto the bus and connect it to the INPUT input of the register group.

[[File:Leg ConnectBus.png]]

Next, we read the inputs. Since there are two parameters, both of which could be inputs, we use switches connected to the output buses of the two register groups.

[[File:Leg ReadInput.png]]

Next, we connect the result (RES) to its corresponding positions (the program counter, output switches).

[[File:Leg ConnectRES.png]]

Finally, we connect the value of the program counter to the bus.

[[File:Leg Counter.png]]