Editing Level/Wire Spaghetti

In this level, we need to build a CPU based on the LEG architecture. This is a significant milestone and quite a challenging one (it took me 20 hours to figure it out at the time).


[[File:Leg.png]]

I propose a feasible implementation solution: Firstly, I encapsulated the register group. Below is a component called "WikiRegisterGroup."
It's important to note that a modified register is utilized here.

[[File:RegisterPlus.png]]

The above has two input signals. The first one controls whether the register outputs to the first bus, and the second one controls whether it outputs to the second bus.
[[File:WikiRegisterGroupa-remake.png]]

This component also accepts an input called "INPUT," which can be used to write to the corresponding register based on the value of "res."
Then, the parameters 1 and parameters 2 are decoded, while the program counter and IN/OUT are separately extracted.

[[File:WikiRegisterGroupa-remake-decode-arg.png]]


The addresses where the results are stored are also decoded, and the corresponding counters and output pins are printed out.


[[File:WikiRegisterGroupa-remake-decode-result.png]]


Assuming you have already completed an ALU with addition functionality, let's proceed from the following diagram:


[[File:Leg BaseLine.png]]


We put the result computed by the ALU onto the bus and connect it to the INPUT input of the register group.


[[File:Leg ConnectBus.png]]


Next, we read the inputs. Since there are two parameters, both of which could be inputs, we use switches connected to the output buses of the two register groups.


[[File:Leg ReadInput.png]]


Next, we connect the result (RES) to its corresponding positions (the program counter, output switches).


[[File:Leg ConnectRES.png]]



Finally, we connect the value of the program counter to the bus and enable RegisterGroup and AlU.



[[File:Leg Counter.png]]