Editing Spec.isa (section)

=== Output bit pattern ===
<pre>
11 000 ccc
</pre>

The bit pattern comes after any virtual operands or assertions.  It defines a sequence of bits that get interpreted as a single big-endian number (which then gets rearranged according to the [[#endianness|endianness] setting).  In this line, space characters (and only space characters) are completely ignored.

Bits can be defined by either individual letters/numbers or explicit operand references.

==== Fixed patterns ====

<code>0</code> and <code>1</code> produce those bits in the output and require those exact bits to be there while disassembling. <code>?</code> also produces <code>0</code> while assembling, but this bit will be ignored when disassembling (once that gets reimplemented).

==== Individual letters ====

All lowercase letters can be used as shortcuts to refer to operands. A letter to refers to the first operand that starts with that letter, with the order being left-to-right in the syntax line and then top-to-bottom for virtual operands.

If a letter appears multiple times, all of those appearances are assigned bits as if they were a single larger field. The bits are assigned LSB-to-MSB to the repeated letters in a right-to-left ordering. For example,

<pre>
test_split_operand
%c = 0b110001
c 0 ccccc 0
</pre>

would result in <code>10100010</code>.

If you use an operand that doesn't support the full length your bit pattern defines, the value will be sign-extended for signed operands and zero-extended for unsigned operands:
<pre>
test_extended_operands
%s:S3 = 0b100
%u:U3 = 0b100
ssssssss uuuuuuuu
</pre>
will result in <code>252 4</code>.

However, the opposite is not true - fields longer than their output format will not be truncated, but will result in an error.  For example:
<pre>
test_overrun
%u:U8 = 32
uuuu0000
</pre>
will result in the error <code>Value 32 outside of range for this 4-bit zero-extended field</code>.

==== Explicit Operand References ====

<pre>
00 %imm[5:0]
</pre>

In addition to individual letters, operands can also be referenced by their full name using the <code>%</code> prefix.  In this case you also need to explicitly tell the assembler which bits to use, using a syntax similar to [[#Bit_slicing|bit slicing]]:
<pre>
%operand[start:end]
</pre>
Unlike the arbitrary bit slicing available when creating virtual operands, the syntax here is much more restrictive:  <code>operand</code> must be a single operand name (instruction operand or virtual), and <code>start</code> and <code>end</code> must be unsigned integer literals.

As with the individual letter syntax, values shorter than the requested bits will be sign- or zero-extended appropriately:
<pre>
test_extended_slicing
%s:S3 = 0b100
%u:U3 = 0b100
%s[7:0] %u[7:0]
</pre>

will result in <code>252 4</code>.

Unlike the single letter syntax, we do not have to worry about overruns with slicing syntax as we're specifying exactly which bits we want, regardless of whether there are more bits available or not.