Editing RS-Latch and the forbidden state (section)

== What do we want to achieve? ==
Let's pretent we start with nothing, but know about techniques to design circuits like K-maps and state machines.

''Side note: State machines already use D-Flip-flops to delay values internally, so one could argue that the whole explanation is kinda circular, but we only use that delay in an abstract way - until we get rid of it''

The whole point of latches and flip-flops is, that we want to build a circuit which behaviour is not only based on the current input values, but also on the things that happened before. So the behaviour is described by not just a combination of current input values ([https://en.wikipedia.org/wiki/Combinational_logic Combinational logic]), but a sequence of input values over time ([https://en.wikipedia.org/wiki/Sequential_logic Sequential logic]).

So what do we want to do?
 1: We have 2 input values S and R and one output Q
 2: If S is {{On}}, we want to set the output to {{On}}
 3: If R is {{On}}, we want to reset the output back to {{Off}}
 4: If neither S nor R is {{On}}, the output keeps the signal that it already has

''Side note: A latch has 2 outputs, but we will get to that later.''

This is the simplest sequential logic that we can build. You can see the ''squential'' part whenever neither R and S in {{On}}, because then the ouput can be anything - depending on whether S or R was {{On}} before in time. And whenever we have sequential logic, we can build a circuit by using state machines! So let's see how it looks like:

[[File:RS firstSM.png]]

Doesn't look so bad... let's build it!
We have a single state variable [[File:Symbol S0.png|20px]], which is {{Off}} in State 0 and {{On}} in State 1. The output is identical to that value. Let's see what circumstances lead to the variable [[File:Symbol S0.png|20px]] beeing {{On}}.

[[File:RS firstSMStateVariable.png]]

Each condition on an arrow is a bit in a K-map, which we can use to build the circuit. So each condition, that we highlighted in our state machine is now turned to {{On}} in our K-map:

[[File:RS firstKV.png]]

So far so good. Since we have a filled K-map now, we can draw blocks and derive the circuit!

[[File:RS firstKVblocks.png]]

{| class="truthtable" style="border: 2px solid darkgray; padding: 2px"
|  || [[File:Symbol S0.png]] || [[File:S_boxed.png]] || [[File:R_boxed.png]]
|-
| [[File:BlueBox.png]] || [[File:On.png|24px]] || [[File:Cross_gray.png|24px]] || [[File:Off.png|24px]]
|-
| [[File:YellowBox.png]] || [[File:Cross_gray.png|24px]] || [[File:On.png|24px]] || [[File:Cross_gray.png|24px]]
|}

[[File:RS circuit1.PNG]]

Just for fun: let's apply De Morgan's law to the OR gate and see what happens:

[[File:RS circuit2.PNG]]

Combine NOTs and ANDs into NANDs 

[[File:RS circuit3.PNG]]

And now reorder it a bit

[[File:RS circuit4.PNG]]

Looks familiar?

[[File:RS NAND table.png]]

We're on the right track (but not quite there, yet)! First of all, let's analyze what happens if both inputs are {{On}}. We can either do that by looking at the state machine, but the truth lies in the K-maps that we turned into our circuit.

[[File:RS firstKVbothON.png]]

Notice: When both inputs S and R are {{On}}, we always switch to state 1. 

'''This does not line up with our state machine!'''

The state machine contains contradictions! 

If we are in state 0, and both inputs are {{On}}, there are two arrows, that we can take: we can either stay in state 0 (because R is {{On}}), or we can go to state 1 (because S is {{On}}).

[[File:RS firstSMContradiction.png]]

The same applies to state 1. Again there are two arrows that we can take, if both inputs are {{On}}:

[[File:RS firstSMContradiction2.png]]

What '''really''' happens in these cases is defined by our K-map (our circuit) that we build. And as you have seen above in our K-map, it always goes to {{On}} - it favors state 1! So now we have to update our state machine and get rid of the contradictions, so that it matches the K-maps.

Let's modify the arrows and get rid of the contradictions:
State 0: If R is {{On}}, then we stay in state 0 only if S is {{Off}}. Because if both are {{On}}, we go to state 1.
State 1: If R is {{On}}, then we go to state 0 only if S is {{Off}}. Because if both are {{On}}, we stay in state 1.

[[File:RS firstSMFinalExplanation.png]]

Now our state machine is nice and clean and describes exactly what we have build.

[[File:RS firstSMFinal.png]]

One thing is strange, though: The circuit contains 2 NAND gates, which are build up symmetrically. However the state machine is NOT symmetrical - it clearly favors state 1! Shouldn't they be both symmetrical?

Yes. (That's another clue, that we are still not finnished, yet)